Receiver and method for concurrent receiving of multiple channels

ABSTRACT

A signal receiving apparatus provides a flexible architecture for single or multiple channel reception capability. According to an exemplary embodiment, the signal receiving apparatus includes a front-end processor and one or more channel recovery elements. The front-end processor includes an A/D converter, a demultiplexer, and one or more filters. The A/D converter receives analog RF signals and converts the analog RF signals to digital RF signals. The demultiplexer Decimates the digital RF signals to generate decimated RF signals. The one or more filters filter the decimated RF signals to generate filtered RF signals. The one or more channel recovery elements process the filtered RF signals to provide baseband signals corresponding to one or more frequency channels.

The present invention generally relates to signal receivers, and moreparticularly, to an apparatus and method for receiving signals whichprovides a flexible architecture for single or multiple channelreception capability and enables, among other things, a lower data ratechannel to be recovered from a higher data rate system.

Signal receivers, such as satellite signal receivers, may be designed toprovide either single or multiple channel reception capability. Withcertain applications, single channel reception capability may besufficient. For example, if cost is a paramount issue for a particularsignal receiver application, it may be desirable to provide only singlechannel reception capability. Alternatively, there may be signalreceiver applications in which multiple channel reception capability isdesired. For example, multiple channel reception capability may bedesirable so that multiple broadcast channels can be receivedsimultaneously. This functionality may, for example, enable consumers towatch one channel and record another channel at the same time.

With conventional signal receivers, the respective architectures usedfor single and multiple channel reception capabilities tend to be quitedifferent from one another. As a result, an architecture designed forsignal receivers having only single channel reception capability may notbe readily used for signal receivers having multiple channel receptioncapability. This incompatibility between architectures is problematic inthat it may require device manufacturers to design and implementcompletely different and independent architectures for single channelreceivers and multi-channel receivers, without benefiting from theeconomies of scale associated with a single architecture. The presentinvention addresses this problem by providing a single, flexiblearchitecture that can be readily used for signal receivers having eithersingle or multiple channel reception capability.

In accordance with an aspect of the present invention, a signalreceiving apparatus is disclosed. According to an exemplary embodiment,the signal receiving apparatus comprises front-end processing means andchannel recovering means. The front-end processing means comprisesanalog-to-digital (A/D) converting means, decimating means, andfiltering means. The A/D converting means receive analog RF signals andconvert the analog RF signals to digital RF signals. The decimatingmeans decimate the digital RF signals to generate decimated RF signals.The filtering means filter the decimated RF signals to generate filteredRF signals. The channel recovering means process the filtered RF signalsto provide baseband signals corresponding to one or more frequencychannels.

In accordance with another aspect of the present invention, a method foroperating a signal receiving apparatus is disclosed. According to anexemplary embodiment, the method comprises steps of receiving analog RFsignals, converting the analog RF signals to digital RF signals,decimating the digital RF signals to generate decimated RF signals,filtering the decimated RF signals to generate filtered RF signals, andprocessing the filtered RF signals to provide baseband signalscorresponding to one or more frequency channels.

The above-mentioned and other features and advantages of this invention,and the manner of attaining them, will become more apparent and theinvention will be better understood by reference to the followingdescription of embodiments of the invention taken in conjunction withthe accompanying drawings, wherein:

FIG. 1 is a block diagram of a signal receiving apparatus according toan exemplary embodiment of the present invention; and

FIG. 2 is a flowchart illustrating steps according to an exemplaryembodiment of the present invention.

The exemplifications set out herein illustrate preferred embodiments ofthe invention, and such exemplifications are not to be construed aslimiting the scope of the invention in any manner.

Referring now to the drawings, and more particularly to FIG. 1, a blockdiagram of a signal receiving apparatus 100 according to an exemplaryembodiment of the present invention is shown. In FIG. 1, signalreceiving apparatus 100 comprises front-end processing means such asfront-end processor 20, and channel recovering means such as channelrecovery elements 40 and 60. The foregoing elements of FIG. 1 may beembodied using integrated circuits (ICs), and any given element may forexample be included on one or more ICs. For clarity of description,certain conventional elements associated with signal receiving apparatus100 such as certain control signals, power signals and/or other elementsmay not be shown in FIG. 1.

Front-end processor 20 is operative to perform various front-end signalprocessing functions of signal receiving apparatus 100. According to anexemplary embodiment, front-end processor 20 performs functionsincluding A/D converting, signal decimating, and filtering functions. Asindicated in FIG. 1, front-end processor 20 comprises A/D convertingmeans such as A/D converter 10, signal decimating means such asdemultiplexer 12, signal delay means such as delay 14, and filteringmeans such as first and second filters 16 and 18. The foregoing elementsof front-end processor 20 may be used regardless of whether signalreceiving apparatus 100 is configured for single or multiple channelreception capability. In this manner, front-end processor 20 provides aflexible architecture that can be readily used for signal receivershaving either single or multiple channel reception capability.

Channel recovery elements 40 and 60 are each operative to performfunctions including channel recovery functions of signal receivingapparatus 100. According to an exemplary embodiment, channel recoveryelements 40 and 60 each recover and provide baseband signalscorresponding to a particular frequency channel. If signal receivingapparatus 100 is receiving signals from a satellite broadcast system,for example, the baseband signals provided by each channel recoveryelement 40 and 60 may correspond to signals from a specific satellitetransponder. Moreover, the baseband signals provided by each channelrecovery element 40 and 60 may include a plurality of broadcastprograms. As indicated in FIG. 1, channel recovery element 40 comprisessignal multiplying means such as first and second signal multipliers 30and 32, signal summing means such as signal summer 34, and auxiliaryfiltering means such as low pass filter (LPF) 36. Similarly, channelrecovery element 60 comprises signal multiplying means such as first andsecond signal multipliers 50 and 52, signal summing means such as signalsummer 54, and auxiliary filtering means such as low pass filter (LPF)56.

For purposes of example and explanation, FIG. 1 shows two channelrecovery elements 40 and 60. In practice however, the number of suchchannel recovery elements may vary according to design choice. Forexample, if multiple channel reception capability is not required, onlya single channel recovery element may be used. Alternatively, ifmultiple channel reception capability for more than two channels isrequired, more than two channel recovery elements may be used.Accordingly, there may be “n” channel recovery elements where “n” is aninteger.

A/D converter 10 is operative to perform an A/D converting function ofsignal receiving apparatus 100. According to an exemplary embodiment,A/D converter 10 receives analog radio frequency (RF) signals includingaudio, video, and/or data signals from one or more signal sources, sucha satellite broadcast system, digital cable broadcast system, digitalterrestrial broadcast system, and/or other system via a signal receivingelement such as an antenna, and converts the analog RF signals todigital RF signals. The analog RF signals may for example bepre-processed (e.g., frequency converted, filtered, etc.) prior to beingreceived by AND converter 10. Also according to an exemplary embodiment,A/D converter 10 performs the A/D converting function in accordance witha clock signal, CLK, having a frequency of 933 MHz. Other clockfrequencies may also be used, including frequencies greater than 1 GHz.

Demultiplexer 12 is operative to perform a signal decimating function ofsignal receiving apparatus 100. According to an exemplary embodiment,demultiplexer 12 serially receives the digital RF signals provided fromA/D converter 10 and demultiplexes the digital RF signals in accordancewith a 1:N decimation rate (where “N” is an integer greater than one) tothereby generate decimated RF signals which are output in a parallelmanner. In other words, demultiplexer 12 is clocked by a clock signalCLK/N, and thereby passes every Nth signal sample to a particular one ofits N outputs. In this manner, demultiplexer 12 enables a lower datarate channel to be recovered from a higher data rate system. Forexample, if signal receiving apparatus 100 is receiving signals from asatellite broadcast system, demultiplexer 12 enables a lower data ratechannel such as a frequency channel corresponding to one satellitetransponder to be recovered from the higher data rate system comprisedof multiple (e.g., 16) satellite transponders.

According to an exemplary embodiment, N is equal to 8, although othervalues may also be used in accordance with design choice. However, itwill be intuitive to those skilled in the art that the value of N hassome practical limitations. For example, if the value of N is too small,there may be a disadvantage in that signal receiving apparatus 100 mustcontinue to perform a lot of high speed serial processing.Alternatively, if the value of N is too large, an adequate frequencyresponse for the particular frequency channel may not be obtained.

Delay 14 is operative to perform a signal delay function of signalreceiving apparatus 100. According to an exemplary embodiment, delay 14provides a one sample delay to the decimated RF signals provided fromdemultiplexer 12 to thereby provide the decimated RF signals in adelayed manner. As indicated in FIG. 1, delay 14 is clocked by the clocksignal, CLK/N.

First and second filters 16 and 18 are operative to perform filteringfunctions of signal receiving apparatus 100. According to an exemplaryembodiment, first filter 16 filters the decimated RF signals providedfrom demultiplexer 12 to thereby generate first filtered RF signals, andsecond filter 18 filters the decimated RF signals having a one sampledelay provided from delay 14 to thereby generate second filtered RFsignals. According to this exemplary embodiment, first and secondfilters 16 and 18 are each clocked by the clock signal CLK/N, and eachincludes a number of filter taps equal to an integer multiple of N. Forexample, first and second filters 16 and 18 may each include N filtertaps. According to this example, first and second filters 16 and 18 eachconstitute one half of a total filter having 2N filter taps, where thefilter taps of first filter 16 constitute the first N filter taps andthe filter taps of second filter 18 constitute the second N filter taps.The selection of tap values for first and second filters 16 and 18 is amatter of design choice. Although not expressly shown in FIG. 1, firstand second filters 16 and 18 receive the decimated RF signals fromdemultiplexer 12 and delay 14, and output the first and second filteredRF signals in a parallel manner, respectively.

First and second signal multipliers 30 and 32 are operative to performsignal multiplying functions of channel recovery element 40. Accordingto an exemplary embodiment, first signal multiplier 30 multiplies thefirst filtered RF signals provided from first filter 16 with consecutivesine and cosine rotational values to thereby generate first multipliedsignals having in-phase (I) and quadrature (Q) components, respectively.Also according to an exemplary embodiment, second signal multiplier 32multiplies the second filtered RF signals provided from second filter 18with consecutive cosine and sine rotational values to thereby generatesecond multiplied signals having I and Q components, respectively. Thenumber of sine and cosine rotational values used by first and secondsignal multipliers 30 and 32 is a function of the number of filter tapsprovided by first and second filters 16 and 18. First and second signalmultipliers 30 and 32 respectively output the first and secondmultiplied signals in a parallel manner in accordance with the clocksignal CLK/N. The sine and cosine values used by first and secondmultipliers 30 and 32 may for example be implemented using a look uptable.

Signal summer 34 is operative to perform signal summing functions ofchannel recovery element 40. According to an exemplary embodiment,signal summer 34 sums the corresponding first and second multipliedsignals provided from first and second multipliers 30 and 32,respectively, to thereby generate frequency converted signals having Iand Q components which are serially output in accordance with the clocksignal CLK/N.

LPF 36 is operative to perform auxiliary filtering functions of channelrecovery element 40. According to an exemplary embodiment, LPF 36filters the frequency converted signals provided from signal summer 34using a low pass filtering technique to thereby generate basebandsignals corresponding to a particular frequency channel. In particular,LPF 36 eliminates signal energy in the frequency range above theparticular frequency channel in order to produce an output that onlycontains signal energy from the particular frequency channel. Asreferred to herein, the term “baseband” may refer to signals that areat, or near, a baseband level. LPF 36 serially outputs the basebandsignals having I and Q components in accordance the clock signal CLK/N.As previously indicated herein, if signal receiving apparatus 100 isreceiving signals from a satellite broadcast system, the basebandsignals output from LPF 36 may correspond to signals from a specificsatellite transponder. Moreover, the baseband signals output from LPF 36may include a plurality of broadcast programs. The baseband signalsoutput from LPF 36 are provided for further processing such as digitaldemodulation, forward error correction (FEC) decoding, and transportprocessing.

First and second signal multipliers 50 and 52, signal summer 54, and LPF56 of channel recovery element 60 are substantially similar to signalmultipliers 30 and 32, signal summer 34, and LPF 36 of channel recoveryelement 40, respectively. Accordingly, for clarity of description thefunctions of these common elements will not be provided again and thereader may refer to the previous descriptions provided herein. However,channel recovery element 60 is operative to recover and provide basebandsignals corresponding to a different frequency channel than channelrecovery element 40. Accordingly, the elements of channel recoveryelement 60 are different in some respects than the elements of channelrecovery element 40. For example, first and second signal multipliers 50and 52 of channel recovery element 60 may use different sine and cosinerotational values than those used by first and second signal multipliers30 and 32 of channel recovery element 40. Moreover, LPF 56 of channelrecovery element 60 may use a different pass band than that used by LPF36 of channel recovery element 40 in order to recover a differentfrequency channel. Such differences between channel recovery elements 40and 60 should be intuitive to those skilled in the art. It is againnoted that the present invention may use one or more channel recoveryelements such as channel recovery elements 40 and 60 depending uponwhether single or multiple channel reception capability is desired.Accordingly, the use of channel recovery element 60 may be optionalbased on design choice. However, if multiple channel receptioncapability is desired, as shown in FIG. 1, channel recovery elements 40and 60 are operative to provide baseband signals corresponding to aplurality of frequency channels in a simultaneous manner.

To facilitate a better understanding of the inventive concepts of thepresent invention, an example will now be provided. Referring to FIG. 2,a flowchart 200 illustrating steps according to an exemplary embodimentof the present invention is shown. For purposes of example andexplanation, the steps of FIG. 2 will be described with reference tosignal receiving apparatus 100 of FIG. 1. The steps of FIG. 2 are merelyexemplary, and are not intended to limit the present invention in anymanner.

At step 210, signal receiving apparatus 100 receives analog RF signalssuch as audio, video, and/or data signals from one or more signalsources, such as a satellite broadcast system, digital cable broadcastsystem, digital terrestrial broadcast system, and/or other system via asignal receiving element such as an antenna.

At step 220, signal receiving apparatus 100 converts the analog RFsignals received at step 210 to digital RF signals. According to anexemplary embodiment, A/D converter 10 converts the analog RF signals todigital RF signals at step 220 in accordance with the clock signal CLK,which may for example exhibit a frequency above or below 1 GHz. Aspreviously indicated herein, the analog RF signals may be pre-processed(e.g., frequency converted, filtered, etc.) prior to being received byA/D converter 10.

At step 230, signal receiving apparatus 100 decimates the digital RFsignals generated at step 220 to thereby generate decimated RF signals.According to an exemplary embodiment, demultiplexer 12 serially receivesthe digital RF signals from A/D converter 10 and demultiplexes thedigital RF signals in accordance with a 1:N decimation rate to therebygenerate the decimated RF signals at step 230. In this manner,demultiplexer 12 passes every Nth signal sample to a particular one ofits N outputs. As previously indicated herein, the decimated RF signalsare output from demultiplexer 12 in a parallel manner in accordance withthe clock signal CLK/N.

At step 240, signal receiving apparatus 100 filters the decimated RFsignals generated at step 230 to thereby generate filtered RF signals.According to an exemplary embodiment, first filter 16 filters thedecimated RF signals provided from demultiplexer 12 to thereby generatefirst filtered RF signals, and second filter 18 filters the decimated RFsignals having a one sample delay provided from delay 14 to therebygenerate second filtered RF signals. In this manner, the first andsecond filtered RF signals provided from first and second filters 16 and18, respectively, collectively represent the filtered RF signalsgenerated at step 240. As previously indicated herein, first and secondfilters 16 and 18 output their respective filtered RF signals in aparallel manner in accordance with the clock signal CLK/N.

At step 250, signal receiving apparatus 100 multiplies and sums thefiltered RF signals generated at step 240 to thereby generate frequencyconverted signals. According to an exemplary embodiment, first signalmultiplier 30 multiplies the first filtered RF signals provided fromfirst filter 16 with sine and cosine rotational values to therebygenerate first multiplied signals having I and Q components,respectively. Similarly, second signal multiplier 32 multiplies thesecond filtered RF signals provided from second filter 18 with cosineand sine rotational values to thereby generate second multiplied signalshaving I and Q components, respectively. As previously indicated herein,first and second signal multipliers 30 and 32 respectively output thefirst and second multiplied signals in a parallel manner in accordancewith the clock signal CLK/N. Signal summer 34 then sums thecorresponding first and second multiplied signals provided from firstand second multipliers 30 and 32, respectively, to thereby generatefrequency converted signals having I and Q components at step 250, whichare serially output in accordance with the clock signal CLK/N. Formultiple channel reception capability, first and second signalmultipliers 50 and 52, and signal summer 54 of channel recovery element60 may also be used to multiply and sum the filtered RF signals at step250.

At step 260, signal receiving apparatus 100 filters the frequencyconverted signals generated at step 250 to thereby provide basebandsignals corresponding to one or more frequency channels. According to anexemplary embodiment, LPF 36 filters the frequency converted signalsprovided from signal summer 34 using a low pass filtering technique tothereby generate baseband signals corresponding to a particularfrequency channel at step 260. As previously indicated herein, LPF 36serially outputs the baseband signals having I and Q components inaccordance the clock signal CLK/N for further processing such as digitaldemodulation, FEC decoding, and transport processing. For multiplechannel reception capability, LPF 56 of channel recovery element 60 mayalso be used to filter corresponding frequency converted signals at step260. In this manner, channel recovery elements 40 and 60 would providebaseband signals corresponding to a plurality of frequency channels in asimultaneous manner at step 260.

In FIG. 2 described above, it is noted that steps 210 to 240 areperformed in the same manner regardless of whether signal receivingapparatus 100 is configured for single or multiple channel receptioncapability. Steps 250 and 260, on the other hand, are scalable and maybe performed in a singular manner for single channel receptioncapability, or in a plural manner for multiple channel receptioncapability.

As described herein, the present invention provides an apparatus andmethod for receiving signals which provides a flexible architecture forsingle or multiple channel reception capability and enables, among otherthings, a lower data rate channel to be recovered from a higher datarate system. While this invention has been described as having apreferred design, the present invention can be further modified withinthe spirit and scope of this disclosure. This application is thereforeintended to cover any variations, uses, or adaptations of the inventionusing its general principles. Further, this application is intended tocover such departures from the present disclosure as come within knownor customary practice in the art to which this invention pertains andwhich fall within the limits of the appended claims.

1. A signal receiving apparatus, comprising: front-end processing meansincluding: analog-to-digital converting means for receiving an analog RFsignal having a plurality of channels and converting said analog RFsignal to a digital RF signal; means for reducing sampling rate of saiddigital RF signal to generate a plurality of decimated RF signals; andmeans for filtering said plurality of decimated RF signals to generate aplurality of filtered RF signals; and channel recovering means forprocessing said plurality of filtered RF signals to provide at least onebaseband signal, each of said at least one baseband signal correspondingto a respective channel.
 2. The signal receiving apparatus of claim 1,wherein said channel recovering means includes: signal multiplying meansfor multiplying said filtered RF signals with rotational values togenerate multiplied signals; signal summing means for summing saidmultiplied signals to generate frequency converted signals; andauxiliary filtering means for filtering said frequency converted signalsto provide said baseband signals.
 3. The signal receiving apparatus ofclaim 1, wherein: said baseband signal corresponds to a plurality offrequency channels; and said channel recovering means provide saidbaseband signals corresponding to said plurality of frequency channelsin a simultaneous manner.
 4. The signal receiving apparatus of claim 1,wherein each of said one or more frequency channels includes a pluralityof broadcast programs.
 5. The signal receiving apparatus of claim 1,wherein said baseband signal includes in-phase and quadraturecomponents.
 6. The signal receiving apparatus of claim 1, wherein eachof said one or more frequency channels corresponds to a specificsatellite transponder.
 7. The signal receiving apparatus of claim 1,wherein said filtering means filter said decimated RF signals in aparallel manner.
 8. A method for operating a signal receiving apparatus,comprising: receiving an analog RF signal; converting said analog RFsignal to a digital RF signal; reducing the sampling rate of saiddigital RF signal to generate a plurality of decimated RF signals;filtering said plurality of decimated RF signals to generate a pluralityof filtered RF signals; and processing said plurality of filtered RFsignals to provide at least one baseband signal each of said at leastone baseband signal corresponding to a respective channel.
 9. The methodof claim 8, wherein said processing step includes: multiplying saidfiltered RF signals with rotational values to generate multipliedsignals; summing said multiplied signals to generate frequency convertedsignals; and filtering said frequency converted signals to provide saidbaseband signals.
 10. The method of claim 8, wherein said basebandsignal corresponds to a plurality of frequency channels and are providedin a simultaneous manner.
 11. The method of claim 8, wherein each ofsaid one or more frequency channels includes a plurality of broadcastprograms.
 12. The method of claim 8, wherein each of said one or morefrequency channels correspond to a specific satellite transponder. 13.The method of claim 8, wherein said baseband signals include inphase andquadrature components.
 14. A signal receiving apparatus, comprising: afront-end processor including: an analog-to-digital converter operativeto receive an analog RF signal and convert said analog RF signal to adigital RF signal; a demultiplexer operative to decimate said digital RFsignal to generate a plurality of decimated RF signals; and one or morefilters operative to filter said plurality of decimated RF signals togenerate a plurality of filtered RF signals; and one or more channelrecovery elements operative to process said plurality of filtered RFsignals to provide at least one baseband signal corresponding to arespective channel.
 15. The signal receiving apparatus of claim 14,wherein each said channel recovery element includes: one or more signalmultipliers operative to multiply said filtered RF signals withrotational values to generate multiplied signals; a signal summeroperative to sum said multiplied signals to generate frequency convertedsignals; and an auxiliary filter operative to filter said frequencyconverted signals to provide said baseband signals.
 16. The signalreceiving apparatus of claim 14, wherein: said one or more channelrecovery elements include a plurality of channel recovery elements; andsaid plurality of channel recovery elements provide said basebandsignals corresponding to a plurality of frequency channels in asimultaneous manner.
 17. The signal receiving apparatus of claim 14,wherein each of said one or more frequency channels includes a pluralityof broadcast programs.
 18. The signal receiving apparatus of claim 14,wherein said baseband signals include in-phase and quadraturecomponents.
 19. The signal receiving apparatus of claim 14, wherein eachof said one or more frequency channels corresponds to a specificsatellite transponder.
 20. The signal receiving apparatus of claim 14,wherein said one or more filters filter said decimated RF signals in aparallel manner.
 21. The signal receiving apparatus of claim 1, whereinsaid filtering means preserves only the spectrum reserved to a desiredchannel.